1. Field of the Invention
The present invention relates to a semiconductor circuit and a photocoupler, and particularly relates to a semiconductor circuit and a photocoupler which operate stably.
2. Description of the Related Art
Generally, a power MOS transistor is used in a half-bridge circuit, and a gate-source withstand voltage VGSS and a drain-source withstand voltage VDSS are different in this power MOS transistor. Therefore, it becomes necessary to provide a protection circuit of some kind in the power MOS transistor. Since the gate-source withstand voltage VGSS is generally lower than the drain-source withstand VDSS, it is common to protect a gate insulating film of the power MOS transistor by inserting clamp elements such as Zener diodes in parallel between a gate and a source thereof.
In a discrete IC, the gate of the power MOS transistor is protected by forming a Zener diode made of polysilicon inside the power MOS transistor. In recent years, various manufacturers launch ICs each having a built-in power MOS transistor through an IC process, but the Zener diode made of polysilicon is not used because of a large leakage current, and a normal Zener diode is usually used as a clamp element.
FIG. 1 shows a sectional view of a Zener diode ZD1. As shown in FIG. 1, the Zener diode ZD1 is formed in an N-type element forming region 14 which is isolated by a P-type semiconductor substrate 10 and a P-type isolation diffusion layer 12. By these semiconductor substrate 10 and isolation diffusion layer 12, the Zener diode ZD1 formed in the element forming region 14 is electrically isolated from other elements.
A P-type anode region 20 is formed in the surface side of the element forming region 14 by diffusion process, and a PN junction is formed between this P-type anode region 20 and the N-type element forming region 14. Namely, the N-type element forming region 14 constitutes a cathode region. An anode electrode 22 which electrically connects with the anode region 20 is formed on the surface of the anode region 20. An N+-type buried impurity region 24 having a higher concentration than the element forming region 14 is formed between the semiconductor substrate 10 and the element forming region 14. Moreover, an N+-type buried impurity region 28 having a higher impurity concentration than the element forming region 14 is formed between the buried impurity region 24 and a cathode electrode 26.
However, the Zener diode ZD1 thus structure parasitically forms a vertical type PNP transistor 30 (hereinafter referred to as a parasitic SubPNP transistor) with the anode region 20, the element forming region 14 and the semiconductor substrate 10 as its emitter, base and collector, respectively. When the cathode electrode 26 has a higher voltage than the anode electrode 22, the Zener diode ZD1 performs a Zener operation, but the parasitic SubPNP transistor 30 does not operate. On the other hand, when the anode electrode 22 has a higher voltage than the cathode electrode 26, the Zener diode ZD1 is turned on as a PN diode, and at the same time, the parasitic SubPNP transistor 30 is also brought into an ON state and operates. As a result, a certain percentage of a current flowing into the anode region 20 leaks to the P-type semiconductor substrate 10.
FIG. 2 is a graph showing the relation between a forward current IF of the Zener diode ZD1 and a subcurrent Isub which flows into the semiconductor substrate 10. FIG. 3 is a circuit diagram showing current measuring points when the forward current IF of the Zener diode ZD1 and the subcurrent Isub are measured, corresponding to the graph in FIG. 2.
From FIG. 2 and FIG. 3, it can be seen that approximately half of the forward current IF flowing through the Zener diode ZD1 leaks to the semiconductor substrate 10 as the subcurrent.
FIG. 4 is a diagram showing an example of a half-bridge circuit in which the Zener diode ZD1 is used as a clamp circuit.
As shown in FIG. 4, a P-type power MOS transistor P1 and ah N-type power MOS transistor N3 are connected at a stage next to a small signal block circuit 41 which treats relatively small signals to constitute a CMOS inverter. Hence, the power MOS transistor P1 and the power MOS transistor N3 complementarily perform on/off operations. Namely, when the power MOS transistor P1 is on, the power MOS transistor N3 is off. Contrary to this, when the power MOS transistor P1 is off, the power MOS transistor N3 is on.
At a stage next to this CMOS inverter, an N-type power MOS transistor N1 as an output element and an N-type power MOS transistor N2 located under the power MOS transistor N1 are connected to thereby constitute a half-bridge output circuit. There is an output terminal Vo between the power MOS transistor N1 and the power MOS transistor N2, and a load circuit is connected to this output terminal. In FIG. 4, this load circuit can be regarded as a load resistance Ro and a load capacitance Co.
A drain of the power MOS transistor N1 is connected, for example, to a supply power source VCC of 30 V, and a source of the power MOS transistor N2 is connected, for example, to a ground GND. The supply power source VCC constitutes a first power source in this embodiment, and the ground GND constitutes a second power source which has a lower voltage than the first power source in this embodiment.
A gate of the power MOS transistor N2 is normally connected to the small signal block circuit 41 via a drive circuit, but in FIG. 4, the drive circuit is omitted. The Zener diode ZD1 is inserted between a gate and a source of the high-side N-type power MOS transistor N1 to connect them.
When the output terminal Vo of the half-bridge circuit in FIG. 4 is high, that is, when the power MOS transistor N1 is on and the power MOS transistor N2 is off, the Zener diode ZD1 performs the Zener operation and it is brought into an on state. Consequently, the gate-source voltage of the power MOS transistor N1 is maintained at a Zener voltage Vz. Incidentally, in this case, the power MOS transistor P1 in the previous stage is on, and the power MOS transistor N3 is off.
Moreover, the Zener diode ZD1 protects the gate of the power MOS transistor N1 also when a signal outputted from the small signal block circuit 41 switches and thereby the output terminal Vo switches from high to low. More specifically, while the voltage of the gate of the power MOS transistor N1 reaches a low level from a high level, both of the power MOS transistors N1 and N2 temporarily become off. While both of these power MOS transistors N1 and N2 are off, the output terminal Vo remains high. Therefore, unless some kind of clamp circuit is inserted between the gate and the source of the power MOS transistor N1, the potential difference between the gate and the source exceeds the gate-source withstand voltage, and thereby a gate insulating film of the power MOS transistor N1 may be destroyed.
In FIG. 4, the Zener diode ZD1 inserted between the gate and the source operates as the PN diode by extracting charge from the load capacitance Co via the load resistance Ro, and the source-gate voltage of the power MOS transistor N1 is maintained at VBE.
However, as described above, when the Zener diode ZD1 operates as a normal diode in the half-bridge circuit in FIG. 4, the parasitic SubPNP transistor 30 operates and thereby part of the current leaks to the semiconductor substrate 10. As shown in FIG. 2, approximately half of the current flowing into the anode electrode 22 leaks to the P-type semiconductor substrate 10.
When the small signal block circuit 41 which operates by small signals is provided at a stage previous to the half-bridge circuit and the small signal block circuit 41 is incorporated in the same IC as shown in FIG. 4, the current which has leaked to the semiconductor substrate 10 changes the GND voltage, whereby there is a possibility of causing the small signal block circuit 41 to malfunction. Furthermore, it is possible that a malfunction signal is outputted from the output terminal Vo to cause a power element at a stage posterior to the half-bridge circuit to malfunction, and that at the worst, the IC or the load circuit is destroyed.